//读操作模块
module read_operate (
    input   wire        clk_20m,
    input   wire        rst_n,
    input   wire        rdempty,
    input   wire        rdfull,         //读启动信号，读一个数，rdfull就消失
    output  reg         rdreq
);

    reg                 cs;             //0:停止状态，1:读数据状态

    always @ (posedge clk_20m or negedge rst_n) begin
        if (!rst_n) begin
            cs <= 0;
            rdreq <= 0;
        end
        else
            case(cs)
                0   : begin
                        if (!rdempty) begin
                            cs <= 1;
                            rdreq <= 1;
                        end
                        else cs <= 0;
                    end
                1   : begin
                        if (rdempty) begin
                            cs <= 0;
                            rdreq <= 0;
                        end
                        else cs <= 1;
                    end
                default: ;
            endcase
    end

endmodule 